24TH Days of Open Systems
Croatian Linux Users’ Conference

31 MAY 2017 - 02 JUNE 2017

FER, Zagreb, Croatia

Video accelerator in 466 lines of VHDL for soft-core processor F32C


F32C is a retargetable, scalar, pipelined, 32-bit processor soft-core which can execute subsets of either RISC-V or MIPS instruction sets. Marko Zec at FER Zagreb started F32C during 2010 as educational platform having a good performing MIPS compatible core with gcc and basic video and audio support. Since 2015 F32C is open sorce, available from https://github.com/f32c. Thanks to members of RADIONA and valuable enthusiasts all over the internet, F32C now has arduino support and fairly rich SOC with hardware acceleration for video, audio, floating point, software-defined-radio and motor control, written in portable VHDL for many FPGA chips from Altera, Lattice and Xilinx. In a short talk time, a simple and efficient 2D video accelerator will be described and shown in action on actual hardware.


Davor Jadrijević

Davor Jadrijević, bsc. electrotechnical engineering and mr. sci. physics doing independent research.


Conference partners

Gold sponsors